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Bugged Out

Bugged Out

By: Siemens Digital Industries Software
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About this listen

 Every chip has bugs — the real question is how fast you can find and fix them. Bugged Out is the bite-sized podcast where we shine a light on the art (and science) of functional verification. In just 10–15 minutes per episode, host Harry Foster, Chief Scientist, Verification, Siemens EDA, sits down with leading innovators, engineers, and researchers to talk about what’s shaping the future of verification — from AI-driven tools to design-for-test, coverage closure, reliability, and more. Expect candid conversations, practical insights, and a few “war stories” from the trenches of debug. Whether you’re a verification engineer, a design lead, or simply curious about how we “get the bugs out” of the chips that power our world, Bugged Out delivers focused, informative conversations designed to fit your busy schedule.Siemens Digital Industries Software
Episodes
  • SDC verification as a first-class asset: A deep dive with Chandu Challapalli

    SDC verification as a first-class asset: A deep dive with Chandu Challapalli
    Jan 27 2026
    In this episode of Bugged Out, Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-Based Timing-Intent Verification with Questa One, Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle. Learn how Questa One brings structure and automation to timing-intent verification—helping teams achieve faster signoff and greater confidence in first-pass silicon success. Key Discussion Points Why Timing Constraints Matter: How SDC files capture design intent—and why ignoring their verification invites silicon risk. What Is Timing-Intent Verification?: A clear explanation of validating clocks, exceptions, and constraints against real design behavior. Finding the Right Balance: The hidden costs of under-constraining versus over-constraining timing. Common SDC Pitfalls: Missing clocks, invalid exceptions, and legacy constraints that mask real bugs. Shifting Left on Timing: Why verifying constraints early—alongside RTL—reduces late-stage surprises. What’s Next: A glimpse into continuous, AI-assisted timing-intent verification and tighter frontend/backend alignment.
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    14 mins
  • FutureCast 2026 — Part 2: Specialization, power, and intelligent verification

    FutureCast 2026 — Part 2: Specialization, power, and intelligent verification
    Dec 16 2025
    In Part 2 of the special FutureCast 2026 holiday series, Harry Foster continues exploring how the semiconductor landscape is rapidly changing — and why the next phase of innovation will be shaped as much by constraints as by breakthroughs. This episode examines the forces pushing systems toward specialization, the growing challenge of data movement, and the rising impact of power, security, and runtime behavior on system correctness. Harry also discusses how verification teams can scale as complexity expands and why agentic AI will become essential to automation and workflow orchestration. Key Discussion Points: Why specialization becomes unavoidable as AI, robotics, and domain-specific compute accelerate The growing impact of data movement bottlenecks and memory-centric architectures How HBM, near-memory compute, analog accelerators, and photonics break legacy abstractions Why physical effects such as thermals and statistical variation now influence functional correctness How verification evolves across cross-domain workflows without overwhelming engineering teams The role of hybrid digital twins in unifying logic, performance, physical behavior, and verification intent Why power ceilings, security boundaries, and model drift become architectural concerns How runtime safety, isolation, and lifecycle monitoring reshape verification planning Why agentic AI shifts from tool enhancement to workflow orchestration and continuous validation Predictions for 2026: AI-assisted verification becomes standard, and data movement emerges as a verification challenge Predictions for 2030: thermal- and statistical-aware verification become standard practice, and agentic AI drives verification infrastructure while curated chiplet marketplaces begin to form
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    8 mins
  • FutureCast 2026 — Part 1: When silicon becomes a living system

    FutureCast 2026 — Part 1: When silicon becomes a living system
    Dec 9 2025
    Join host Harry Foster for a special holiday edition of Bugged Out. In this first episode of the two-part FutureCast 2026 series, Harry steps away from the usual guest interviews to look at how the semiconductor industry is evolving — and why innovation is now happening far above the transistor. This episode explores why modern silicon behaves less like a static product and more like a living, continuously changing system. Harry highlights the technologies driving this shift, from multi-die architectures to software-defined hardware, and explains how verification must expand across the entire product lifecycle. Key discussion points: Why innovation has moved above the transistor How chiplets, hybrid bonding, and HBM are redefining system performance The collapse of traditional design boundaries across logic, timing, thermals, and software Emerging system-level behaviors in multi-die architectures Why these changes reshape verification across physical and logical domains The role of hybrid digital twins in capturing system truth How software-defined products evolve after shipping Why OTA updates become verification events The shift from traditional to lifecycle-aware verification Predictions for 2026: multi-die verification becomes essential, and lifecycle-aware verification becomes mandatory for advanced AI-driven devices Predictions for 2030: hybrid digital twins become foundational, and early chiplet vendors enter the market with curated offerings
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    8 mins
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