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Accelerating DFT Sign-off: Getting the Bugs Out of Complex Chips

Accelerating DFT Sign-off: Getting the Bugs Out of Complex Chips

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 Episode Title: Accelerating DFT Sign-off: Getting the Bugs Out of Complex Chips Host: Harry Foster Guest: Jake Wiltgen, Director of IC Verification Solutions at Siemens EDA ________________________________________ Episode Summary Join host Harry Foster on Bugged Out as he dives deep into the world of functional verification with special guest Jake Wiltgen from Siemens EDA. This episode explores the critical role of Design for Test (DFT) in ensuring high-quality silicon for today's most complex chips. Jake shares his journey into DFT, explains why it's more crucial than ever, and highlights key insights from his whitepaper, "Accelerating DFT sign-off with Questa One." Discover how new verification technologies are tackling bottlenecks, addressing mega-trends in chip design, and evolving to meet the challenges of silicon reliability and in-system test. ________________________________________ Key Discussion Points The Mission of Bugged Out: Harry introduces the podcast's goal: to bring candid conversations about finding and fixing bugs in complex chips. Meet the Expert: Jake Wiltgen, an expert in safety-critical systems, functional safety standards, and DFT, shares his extensive industry experience. What is DFT? Jake breaks down Design for Test in an accessible way, explaining its primary objective: to deliver high-quality, functionally correct silicon by building in capabilities to test for manufacturing defects. Jake's Journey into DFT: Discover how Jake got pulled into the world of DFT, driven by growing needs for fault-grading and addressing long-running serial simulations. Tackling the Tapeout Bottleneck: Learn why DFT sign-off often becomes a bottleneck during the critical period between netlist drop and tapeout, and how Questa One helps accelerate these essential simulations. Mega-Trends in DFT: Harry and Jake discuss the impact of technology scaling, design scaling, and system scaling on engineers, noting that the growing volume of DFT verification at both block and top levels is a major challenge. Evolving Challenges: Reliability and Aging Silicon: Explore how the objectives of DFT remain the same, but the methods have evolved dramatically due to embedded AI, autonomous vehicles, and angstrom-scale technology nodes. In-System Test (IST) in Practice: Jake paints a vivid picture of IST, illustrating its benefits in data centers (predicting silicon failure) and automotive (detecting safety-critical system failures before they cause harm). ________________________________________ Resources Mentioned White Paper: "Accelerating DFT sign-off with Questa One" by Jake Wiltgen.
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