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3D IC

3D IC

By: Siemens Digital Industries Software
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As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing. 3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing. Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures. In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including: Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling Mainstream adoption of 3D IC—key challenges and breakthroughs Optimizing micro-architecture and integration platforms for performance and efficiency Strategic planning of chiplets and interposers for hierarchical device integration Leveraging early predictive multi-physics analysis to enhance design accuracy Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP) Exploring glass substrates for superior electrical and thermal performance Developing test-vehicles and daisy chain designs for architectural validation Ensuring reliability and manufacturability in 3D IC heterogeneous integration Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems Managing thermal challenges in stacked die architectures Subscribe now and stay ahead in the world of 3D IC. Learn more: Siemens 3D IC Packaging SolutionsSiemens Digital Industries Software Politics & Government
Episodes
  • Zero Trust in Silicon: The New Security Imperative for Chiplet-Based 3D ICs

    Zero Trust in Silicon: The New Security Imperative for Chiplet-Based 3D ICs
    Jul 1 2026
    How do you secure a chip when the chip itself is made up of dies from multiple vendors and you can’t automatically trust any of them? What you’ll learn... (02:00) Chris’s background: 30 years of all-round experience (03:00) What is hardware security? (05:30) Why hardware security is critical now & examples of security breaches (08:30) Current security practices and required changes (08:27) How security has traditionally been done — and what has to change (11:13) The shift to a system-level view of security, especially in chiplet-based design (11:00) Security challenges in 3D IC architectures (12:30) How can companies maintain IP integrity and prevent tampering throughout the 3D IC lifecycle? (15:30) Maintaining IP integrity in 3D IC supply chains (17:40) The Crypto Quantique / Siemens joint solution (20:11) The most important thing designers and system architects should understand about hardware security. More about this episode... In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Chris Jones, Director of Applications at Crypto Quantique, about what it takes to build hardware security into silicon from the ground up — and why the move to 3D IC architectures makes that challenge dramatically harder. Chris opens by explaining what hardware security actually means at the silicon level: not just encryption, but a fixed, immutable boot sequence that runs from ROM every time a device powers on, verifying that firmware is signed and untampered before any application code is allowed to execute. It's a foundation that must be designed in not bolted on after the fact. When chiplets from multiple vendors are stacked in a single package, every die-to-die interface becomes a potential attack surface. Chris explains why the industry must adopt a zero trust model — no chiplet should be assumed trustworthy simply because it's in the stack — and how physically unclonable functions (PUFs) enable each die to cryptographically prove its identity without ever exposing a secret key. Chris and Tova also explore the industry forces pushing security up the agenda: the Trusted Computing Group and GlobalPlatform standardizing hardware roots of trust; NIST maintaining verified cryptographic standards; and the EU Cyber Resilience Act, requiring built-in security, OTA updates, and documented risk analysis for all connected products by December 2027. The episode closes with the joint solution Crypto Quantique has developed with Siemens: QRoot Lite, a lightweight root-of-trust IP block now integrated into Siemens' Tessent EDA toolchain, automatically securing IJTAG-based DFT interfaces during manufacturing and ensuring test sequences can only be run by authorized parties. For anyone working in 3D IC design, chiplet architecture, semiconductor security, or EDA, this episode offers a grounded, practical view of what it means to take hardware security seriously — from the first blank sheet of paper all the way through manufacturing. Ideal for: 3D IC architects, SoC and ASIC designers, semiconductor security engineers, EDA tool users, IP vendors, system integrators, and anyone navigating the hardware security requirements of connected devices and 3D IC supply chains. Connect with Tova Levy LinkedIn Website Connect with Chris Jones LinkedIn Website
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    23 mins
  • Beyond the Data Pipe: Why Connectivity IP Is Now the System-Critical Layer in Every 3D IC

    Beyond the Data Pipe: Why Connectivity IP Is Now the System-Critical Layer in Every 3D IC
    Jun 24 2026
    What does it actually mean for connectivity IP to stop being a supporting function — and become the layer that determines whether a 3D IC delivers on its promise? What you’ll learn... (02:45) Archana's background: semiconductor IP, high-speed clocking, and AI memory subsystems (03:49) Alphawave Semi's role in 3D IC — and why the interconnect layer is now foundational (05:40) 3D IC integration headaches: signal integrity, power delivery, and thermal hotspots (07:59) IP development for 3D ICs: co-optimizing with packaging, interposers, and photonics (10:02) Friction points: methodology inertia, ecosystem immaturity, and standardization vs. customization (12:26) Balancing performance, reliability, and manufacturability — and Alphawave Semi's validation approach (14:51) The magic wand pick: open chiplet interoperability and solving thermal constraints (17:27) What's accelerating now: UCIe adoption, cross-chain collaboration, photonics, and advanced packaging More about this episode... In this Season 3 premiere of the Siemens 3D IC Podcast, new host Tova Levy speaks with Archana Cheruliyil, Principal Product Marketing Manager at Alphawave Semi, a Qualcomm company, about what it really takes to develop IP for 3D ICs — and why connectivity has shifted from a background function to a system-defining one. Alphawave Semi's portfolio spans UCIe die-to-die interconnect, HBM memory interfaces, PCIe, CXL, and custom silicon, all optimized for the disaggregated architectures that 3D IC design demands. Archana places connectivity IP at the center of the challenge: in stacked, chiplet-based designs, the interconnect layer directly determines system performance, power efficiency, and scalability. Signal integrity behaves differently in dense 3D electromagnetic environments, power delivery must be managed vertically across multiple dies, and thermal hotspots in stacked logic have no easy escape path — forcing teams into system-level trade-offs across signal, power, thermal, and packaging simultaneously. Adding photonics into the mix raises the stakes further, combining different materials and design constraints within the same package. On the market side, Archana unpacks the tension between open standards like UCIe — which enable interoperability but can't always keep pace with customer demands — and the highly customized solutions that drive real differentiation. Siemens is highlighted as a key emulation and system-level validation partner, helping teams understand full-system behavior before silicon is produced. The episode closes with Archana's vision for what would unlock the next phase of 3D IC adoption: a truly open chiplet marketplace that frees engineering cycles for innovation rather than integration reinvention — and progress on thermal management to enable deeper stacking across a broader range of applications. Ideal for: 3D IC architects, silicon IP designers, advanced packaging engineers, chiplet ecosystem participants, EDA users, and anyone navigating the shift from monolithic SoC design to heterogeneous, disaggregated integration. Connect with Tova Levy LinkedIn Website Connect with Archana P Cheruliyil LinkedIn Alphawave’s website
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    21 mins
  • From 2.5D to True 3D IC: What’s Driving the Next Wave of Integration

    From 2.5D to True 3D IC: What’s Driving the Next Wave of Integration
    Sep 18 2025
    How do you transition from today’s 2.5D systems into tomorrow’s true 3D IC architectures — while balancing cost, performance, and thermal demands? What you’ll learn… Where hyperscalers and AI accelerator developers are leading the 3D IC adoption curve. Why design enablement and ecosystems are still evolving for mainstream adoption. The tipping points that push companies toward 2.5D/3D IC designs. The new methodology requirements: system-centric, predictive, shift-left modeling. Why siloed design teams can’t meet the demands of advanced 3D IC. How Siemens’ portfolio and AE expertise help customers adapt tools, methods, and organizations for success. What you’ll discover… (01:40) Current state of 3D IC adoption: hyperscalers, AI accelerators, and beyond. (04:20) 3D VS 2.5D design and (hybrid bonding, stacking, bridges). (05:30) Why customers want to learn more about 3D IC design. (06:50) Why do customers move over to 3D IC design? (08:25) Challenges in 3D IC design. (10:20) Methodology shifts: early system-level planning and predictive modeling (13:30) Siemens’ broad portfolio, roadmap collaboration, and multi-physics modeling (15:45) The 5-year outlook: chiplet standards, system-on-wafer, and power/thermal battles More about this episode… In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Kevin Rinebold, 3D IC Packaging and Account Technology Manager at Siemens EDA. With over 35 years of customer-facing experience, Kevin shares insights into the evolution of advanced packaging, chiplet integration, and the methodologies needed for the next wave of 3D IC adoption. The discussion covers how hyperscalers are driving AI and high-performance compute with 2.5D and emerging 3D approaches, why design enablement remains uneven across the supply chain, and what’s required to balance thermal, power, and signal considerations at scale. Kevin emphasizes that 3D IC isn’t just a technical challenge; it’s an organizational shift toward integrated, cross-disciplinary collaboration. He also highlights Siemens’ role in enabling customers to “shift left,” evaluate tradeoffs early, and leverage a broad portfolio of tools and expertise to meet the complexity of future 3D IC designs. Looking ahead, Kevin points to maturing chiplet standards, system-on-wafer architectures, and the ongoing battle to get power in and heat out of dense 3D IC stacks. Ideal for: IC packaging engineers, 3D IC architects, chiplet designers, substrate fabricators, and verification professionals navigating the shift from 2.5D to 3D integration. Connect with John McMillan LinkedIn Website Connect with Kevin Rinebold LinkedIn Website
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    18 mins
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